Smartphone is next stop for PCI Express

PCI Express, the I/O backbone of PCs and servers, is getting a low-power extension that will take it into Ultrabooks, tablets and smartphones starting next year. The enhanced interconnect will draw two to four times less power while helping mobile devices link to high-performance peripherals such as 60-GHz wireless networking controllers and solid-state drives.

The PCI Special Interest Group expects to approve by the end of the year a new version of its low level software for PCIe 3.0. The code will run on the M-PHY physical layer chips defined by the MIPI Alliance that creates handset interfaces.

The two groups signed a deal Monday (Sept. 10), cementing their collaboration. The PCI SIG will also create a version of its next-generation PCIe 4.0 software for M-PHY.

“We’ve been chasing for months the Holy Grail of getting to a lower power version of PCI Express because we know that’s where the volume is and where the users are,” said Al Yanes, chairman of the PCI SIG.

Specifically, the PCI SIG will define a new variant of its physical link layer software to run the M-PHY. The code will enable multiple asymmetrical lanes, dynamic bandwidth negotiation and lower electromagnetic interference.

“We are making PCI Express mobile friendly,” said Brian Carlson, vice chairman of the MIPI Alliance.

Last year, a senior Marvell engineering manager called for a mobile interconnect to link his applications processor to an external 802.11ac controller. The link needs to deliver 1.1Gbits/s while consuming less than 38 milliwatts on a 1.8-volt supply, he said.

The new M-PHY combined with PCI Express addresses that need, said Carlson. M-PHY was first defined in April 2011 at 1.25 Gbits/s, an update released in June 2012 runs at 2.9 Gbits/s and a third generation coming next year will hit up to 5.8 Gbits/s.

The link is defined over copper traces at up to 30 cm and over optical lengths up to five meters. For its part, PCIe 3.0 supports up to 8 GTranfers/second.

As many as three billion devices using MIPI interfaces could ship in 2012, said Carlson. Many of them use an older D-PHY link, running at about 500 Mbits/s, geared for mobile displays and cameras.

The new variant of PCIe over M-PHY addresses active power, the biggest consumer of energy. The PCI SIG released in June an addition to its PCIe 3.0 spec addressing idle power, a technology Intel incorporated into the design of its next-generation processor, Haswell.

Transaction Layer (TL) of PCI Express

This layer’s primary responsibility is to create PCI Express request and completion transactions. It has both transmit functions for outgoing transactions, and receive functions for incoming transactions. On the transmit side, the Transaction Layer receives request data (such as “read from BIOS location FFF0h”) or completion data (“here is the result of that read”) from the device core, and then turns that information into an outgoing PCI Express transaction. On the receive side, the Transaction Layer also accepts incoming PCI Express transactions from its Data Link Layer (refer to fig.). This layer assumes all incoming information is correct, because it relies on its Data Link Layer to ensure that all incoming information is error-free and properly ordered.

PCI Express: "A Layered Architecture"

PCI Express is a layered protocol, consisting of a transaction layer, a data link layer, and a physical layer. The Data Link Layer is subdivided to include a media access control (MAC) sublayer. The Physical Layer is subdivided into logical and electrical sublayers. The Physical logical-sublayer contains a physical coding sublayer (PCS). (Terms borrowed from the IEEE 802 model of networking protocol.)

Configuration/Operating System Layer —Leverages the standard mechanisms defined in the PCI Plug-and-Play specification for device initialization, enumeration, and configuration. This layer communicates with the software layer by initiating a data transfer between peripherals or receiving data from an attached peripheral. PCI Express is designed to be compatible with existing operating systems, but future operating system support is required for many of the technology’s advanced features.

Software Layer —Generates read and write requests to peripheral devices. PCI Express maintains initialization and runtime software compatibility with PCI. Like PCI, the PCI Express initialization model allows the operating system to discover add-in hardware devices and allocate system resources. PCI Express retains the PCI configuration space and the programmability of I/O devices. In fact, all operating systems will boot without modification on a PCI Express system. The PCI runtime software model is also preserved, enabling existing software to execute unchanged.

Transaction Layer —Transports read and write requests from the software layer to the link layer using a packet-based protocol, and matches response packets to the original software requests. The transaction layer supports 32-bit and extended 64-bit memory addressing. It also supports PCI memory, I/O, and configuration address spaces, as well as a new message space for in-band messages such as interrupts and resets. This message space eliminates the need for numerous PCI and PCI-X sideband signals.

Link Layer —Adds sequencing and error detection cyclic redundancy codes (CRCs) to the data packets to create a reliable data transfer mechanism between the system chip set and the I/O controller.

Physical Layer —Implements the dual simplex PCI Express channels. Implementations are flexible and various technologies and frequencies may be used. In this way, initial silicon technology can be replaced easily with future implementations that are backward compatible. For example, fiber-optic technology might be used to increase the data transfer rate.

Mechanical Layer —Defines various form factors for peripheral devices.